The present invention relates to the testing of digital circuits and systems in using pseudo-random scan test techniques, and particularly to the capability of checking the operability of the input/output circuits of such circuits and systems during the test period.
Recent advances in the art of semiconductor circuit fabrication, particularly in the area of manufacturing components for digital computer systems, have seen a significant increase in the amount of circuitry that can be formed on any given area of semiconductor. In addition, while circuit density per semiconductor area has increased, chip size (i.e., the semiconductor area available for holding the circuitry) has also increased, resulting in integrated circuit chips carrying an enormous amount of digital circuitry. These are often termed large-scale integrated (LSI) or very large-scale integrated (VLSI) circuitry.
Earlier in the chronological development of integrated circuits, testing was relatively straightforward: Known test signals were applied to the inputs of the circuit, varied, and the outputs monitored. On the simpler, less integrated circuitry then available, this technique was easy to use, and proved quite useful. However, as integrated circuit densities increased, including the number of elemental storage units (e.g., latches, flip-flops, registers and the like) more sophisticated techniques became necessary.
One such technique in use today is referred to as pseudo-random "scan testing." This technique requires the elemental memory units forming a part of the integrated circuit to be designed to selectively function in one of two modes: A first or "normal" mode in which they operate as primarily designed, i.e., flip-flop or register; and a second, "test" mode in which a number of the elemental memory stages are connected in series to form one or more extended shift registers or, as they are more commonly called, "scan lines." Pseudo-random bit patterns are then scanned (loaded) into the scan lines, the system under test allowed to operate in its normal configuration for one clock time, and the system returned to its test state so the content of the scan lines scanned (shifted) out and analyzed (usually by comparing it to known or standard patterns). The operability of the tested system is thereby established. Examples of the foregoing may be found in U.S. Pat. Nos. 4,718,065, 4,534,028, and 4,827,476.
Pseudo-random scan testing to which the present invention is directed, as the term implies, involves applying pseudo-random patterns to any input circuits of the system under test, and monitoring the output of any output circuits. While this technique of testing provides many benefits, such as a cost effective test method without need to form special test vectors in advance, there are problems. One such problem is the difficulty, if not inability, to predict in advance the state that certain input/output circuits will assume during testing. For example, certain circuits of the system under test may be capable of operating in one of two modes: Input or output. To date, insofar as is known, pseudo-random scan test techniques do not provide complete confidence that portions of such input/output circuit are tested. The reason stems from the inability to easily predict the input-output direction of the circuit; during scan test time bit patterns (which, it will be remembered, are pseudo-random) must be supplied to the input section, and the output section monitored. Since, during the test period, there is usually no easy way to know what state (i.e., input or output) the input/output circuit will be, applying a test signal at the same time the input/output circuit is functioning as an output produces indeterminate results. For example, assume the tester applies a logic ZERO while the input/output circuit is in an output mode of operation, providing a logic ONE. The monitored voltage at the terminal pin connected to the input/output circuit may read a logic Zero at one time, a logic ONE at an other time; that is, it is never certain that a logic ONE or ZERO will appear under such conditions.
This uncertainty has resulted in such dual-function circuits not being completely tested.
Accordingly, there is a need for including in scan test techniques a methodology that can also monitor and check the operability of such dual-function input/output circuitry.